Critical Issues of Wafer Level Chip Scale Package (WLCSP)

ABSTRACT:Some of the critical issues of wafer level chip scale package (WLCSP) are mentioned and discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the important parameters such as wafer-level redistribution, wafer-bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Only solder-bumped with pad-redistribution WLCSPs are considered in this study.

INTRODUCTION:There are at least two major reasons why directly attaching the solder bumped flip chip on organic substrates is not popular yet [1, 2]. Because of the thermal expansion mismatch between the silicon chip and the epoxy PCB, underfill encapsulant is usually needed for solder joint reliability. However, due to the underfill operation, the manufacturing cost is increased and the manufacturing throughput is reduced. In addition, the rework of an underfilled flip chip on PCB is very difficult, if it is not impossible.
The other reason is because the pitch and size of the pads on the peripheral-arrayed chips are very small and pose great demands on the supporting PCB. The high-density PCBs with sequential build-up circuits connected through microvias are not commonly available at reasonable cost yet.
Meantime, a new class of packaging called wafer level chip scale package (WLCSP) provides a solution to these problems [1 – 15]. There are many different kinds of WLCSP, for examples, eight different (ChipScale, EPIC, FCT, Fujitsu, Mitsubishi, National Semiconductor, Sandia National Laboratories, and ShellCase) companies’ WLCSP are reported in [2] and six different (EPS/APTOS, Amkor/Anam, Hyundai, FormFactor, Tessera, and Oxford) companies’ WLCSP are reported in [1]. Just like many other new technologies,

The infrastructure of WLCSP is not well established
The standard of WLCSP is not well established
WLCSP expertise is not commonly available
Bare wafer is not commonly available
Bare wafer handling is delicate
High cost for poor-yield IC wafers
Wafer bumping is still too costly
High cost for low wafer-bumping yield, especially for high-cost dies
Wafer-level redistribution is still too costly
High cost for low wafer-level redistribution yield, especially for high-cost dies
Troubles with System Makers if the die shrinks
Test at speed and burn-in at high temperature on a wafer are difficult
Single-point touch-up on the wafer is difficult
PCB assembly of WLCSP is more difficult
Solder joint reliability is more critical
Alpha particles produce soft errors by penetrating through the lead-bearing solder on WLCSP
Impact of lead-free solder regulations on WLCSP
Who should do the WLCSP? IC Foundries or Bump Houses?
What are the cost-effective and reliable WLCSPs and for what IC devices?
How large is the WLCSP market?
What is the life cycle of WLCSP?

WLCSP COSTS

Since 100% perfect wafers cannot be made at high volume today, the true IC chip yield (YT) plays the most important role in cost analysis. Also, the physical possible number of undamaged chips (Nc) stepped from a wafer is need for cost analysis, since (YTNc) is the number of truly good die on a wafer. Nc is given by [1, 2, 16]
where
A = xy (2)
and
In Equations (1) – (3), x and y are the dimensions of a rectangular chip (in millimeters, mm) with x no less than y; q is the ratio between x and y; f is the wafer diameter (mm); and A is the area of the chip (in square millimeters, mm2). For example, for a 200 mm wafer with A = 10 x 10 = 100 mm2, then Nc ~

Wafer Redistribution Costs

Wafer-level redistribution is the heart of the WLCSPs. The cost of wafer-level redistribution is affected by the true yield (YT) of the IC chip, the wafer-level redistribution yield (YR), and the good die cost (CD). The actual wafer-level redistribution cost per wafer (CR) is:
CR=CWR+(1–YR)YTNCCD (4)
where CWR is the wafer-level redistribution cost per wafer (ranging from $50 to $200), YR is the wafer-level redistribution yield per wafer, CD is the good die cost (not the cost of an individual die on the wafer), Nc is given in Equation (1), and YT is the true IC chip yield after at-speed/burn-in system tests (or individual die yield). Again, it can be seen that the actual wafer-level redistribution cost per wafer depends not only on the wafer-level redistribution cost per wafer but also on the true IC chip yield per wafer, wafer-level redistribution yield per wafer, and good die cost.
Wafer-level redistribution yield (YR) plays a very important role in WLCSP. The wafer-level redistribution yield loss (1-YR) could be due to: (1) more process steps; (2) wafer breakage; (3) wafer warping; (4) process defects such as spots of contamination or irregularities on the wafer surface; (5) mask defects such as spot, hole, inclusion, protrusion, break, and bridge; (6) feature-size distortions; (7) pattern mis-registration; (8) lack of resist adhesion; (9) over etch; (10) undercutting; (11) incomplete etch; and (12) wrong materials. It should be noted that wafer-level redistribution are not reworkable. It has to be right the first time, otherwise, someone has to pay for it!
The uses of Equations (1) and (4) are shown in the following examples. If the die size of a 200 mm wafer is 100 mm2, true IC chip yield per wafer is 80% (since the importance of YT has been shown in [16, 17], only one value of YT will be consider in this study), wafer-level redistribution yield per wafer is 90%, wafer-level redistribution cost per wafer is $100, and the die cost is $100 (e.g., microprocessors), then from Equation (1), Nc = 255, and from Equation (4), the actual wafer-level redistribution cost per wafer is $2140. For the same size of wafer if the die cost is $5 (e.g., memory devices), then the actual wafer-level redistribution cost per wafer is $202. It is noted that for both cases, the actual wafer-level redistribution cost per wafer is much higher than the wafer-level redistribution cost (CWR = $100)!
On the other hand, if the wafer-level redistribution yield is increased from 90% to 99%, then the actual cost for redistributing the microprocessors wafer is reduced from $2140 to $304 and for redistributing the memory wafer is reduced from $202 to $110.2. Thus, wafer-level redistribution yield plays an important role in the cost of wafer-level redistribution and the wafer-level redistribution houses should stride to make YR > 99%, especially for expensive good dies

Wafer Bumping Costs

Wafer bumping is the heart of solder-bumped WLCSPs. The cost of wafer bumping is affected by YT, CD, YR and the wafer-bumping yield (YB). The actual wafer bumping cost per wafer (CB) is:
CB=CWB+(1–YB)YRYTNCCD (5)
where CWB is the wafer bumping cost per wafer (ranging from $25 to $250), YB is the wafer-bumping yield per wafer, YR is the wafer-level redistribution yield per wafer, CD is the good die cost, Nc is given in Equation (1), and YT is the true IC chip yield after at-speed/burn-in system tests (or individual die yield). Again, it can be seen that the actual wafer bumping cost per wafer depends not only on the wafer-bumping cost per wafer but also on the true IC chip yield per wafer, wafer-bumping yield per wafer, good die cost, and wafer-level redistribution yield per wafer.
Just like YR, wafer bumping yield (YB) plays a very important role in wafer bumping. The wafer bumping yield loss (1-YB) could be due to: (1) wrong process;, (2) different materials; (3) too tall or short of a bump height; (4) not enough shear strength; (5) un-even shear strength; (6) broken wafers or dies; (7) solder bridging; (8) damaged bumps; (9) missing bumps; and (10) scratch of the wafer.
For the pervious example, if the wafer-bumping yield per wafer is 90% and wafer bumping cost per wafer is $120, then the actual wafer bumping costs per (the microprocessors) wafer are, respectively, $1956 if YR = 90% and $2139.6 if YR = 99%, and the actual wafer bumping costs per (the memory) wafer are, respectively, $211.8 if YR = 90% and $220.98 if YR = 99%. Again, it should be noted that the actual wafer-bumping cost per wafer is much higher than the wafer-bumping cost (CWB = $120).
On the other hand, if the wafer-bumping yield is increased from 90% to 99%, then the actual costs for bumping the microprocessors wafer are, respectively, $303.6 if YR = 90% and $321.96 if YR = 99%, and the actual costs for bumping the memory wafer are, respectively, $129.18 if YR = 90% and $130.1 if YR = 99%. Thus, wafer-bumping yield plays an important role in the cost of wafer bumping and the wafer bumping houses should stride to make YBYR > 99%, especially for expensive good dies. If there is no wafer-level redistribution, then there is no wafer redistribution yield loss, i.e., YR = 1, then Equation (5)

SUMMARY

More than 20 different critical issues of WLCSP have been mentioned. The most important issue (cost) of WLCSP has been analyzed in terms of the true IC chip yield, wafer-level redistribution yield, wafer-bumping yield, wafer-level underfill yield, and die size and cost. Also, useful equations in terms of these parameters have been presented and demonstrated through examples. Some important results are summarized as follows.
IC chip yield (YT) plays the most important role in WLCSP. If YT is low for a particular IC device, then it is not cost-effective to house the IC with WLCSP, unless it is compensated for by performance, density, and form factor.
Wafer-level redistribution yield (YR) plays the second most important role in WLCSP. Since this is the first post wafer processing after the IC FAB, the wafer-level redistribution houses should stride to make YR > 99% (99.9% is preferred). Otherwise, it will make the subsequent steps very expensive by wasting the material and process on the damage dies.
Wafer-bumping yield (YB) plays the third most important role in WLCSP. The wafer bumping house should strive to make YRYB > 99% (99.9% is preferred) to minimize the hidden cost, since they cannot afford to damage the already redistributed good dies.
Based on cost and process points of view, wafer-level underfill is not a good idea for solder-bumped flip chip on low-cost substrates.